1. Field of the Invention
The present application relates to methods of making integrated circuits. More specifically it relates to methods of fabricating semiconductor devices using sidewall image transfer (SIT) patterning processes.
2. Description of the Related Art
Manufacturing of semiconductor devices generally involves performing various steps of device patterning processes. For example, the manufacturing of a semiconductor device may start with using computer aided design (CAD) generated device patterns and then duplicating those patterns onto a substrate to form individual semiconductor devices. The duplication process may involve using various exposing techniques (e.g. photolithography) in combination with a variety of subtractive (e.g. etching) and additive (e.g. deposition) material processing steps.
For example, in a photolithography process, a layer of photoresist material may be first applied to a substrate, and then selectively exposed using a predetermined device pattern. More specifically, the photoresist may be deposited on the substrate, then portions of the photoresist selectively exposed to light or other ionizing radiation (e.g., ultraviolet, electron beam, x-ray, etc) using the predetermined device pattern. The light or other ionizing radiation can cause the photoresist to undergo a change in solubility with respect to certain chemical solutions. After the photoresist has been exposed using the light or other ionizing radiation, it can then be developed using a developer solution to remove non-irradiated (in so-called “negative resist situations”) or the radiated (in so-called “positive resist situations”) portions of the photoresist layer to reproduce the predetermined device pattern in the photoresist. Further, the photoresist pattern subsequently may then be copied or transferred to the substrate underneath the photoresist pattern.
As the space available for semiconductor devices has continued to decrease, semiconductor manufacturers have been challenged to meet the demand for ever increasing device density. One technique for sub-80 nm pitch patterning has been to use a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer, to achieve a pattern density twice that achievable using previous techniques. A conventional SIT process involves forming a mandrel layer on a hard mask layer then forming a spacer layer conformably over the mandrel and hard mask layers. Then, the spacer is etched back followed by pulling out the mandrel layer. In certain applications a series of layers of an Organic Planarization Layer (OPL), a Silicon Anti-reflective Coating (SiARC) layer, and a photoresist layer are then formed over the spacer layer in sequence and the photoresist layer patterned to form a block area and a non-block area. After the photoresist layer is patterned, the photoresist layer is etched and removed in the non-block area. Then metal hard mask etching process is performed during which the SiARC layer is first etched back to expose the OPL layer in the block area. Then, the metal hard mask in the non-block area is etched simultaneously with the spacer and OPL in the block area. Finally, the OPL in the block area is removed by an ashing process.
However, there can be some problems with the above process. For example, as discussed in more detail below, a low temperature silicon dioxide (LTO) can be used as the spacer. In such a situation, the LTO spacer inadvertently also can be etched back during the SiARC etch back step because LTO and SiARC films have similar material properties and etch at similar rates. This inadvertent etching of the LTO spacer can cause the spacer height to be reduced and the side-profile of the spacer to be rounded. As a result, the short, round-shaped spacer can cause a poor metal hard mask etching profile and produce critical dimension (CD) change. This poor metal hard mask profile can reduce the yield and reliability of the resulting semiconductor device due to degradation of interconnects formed by the SIT process.
Attempts to solve this problem include using SiN as the spacer film, rather than LTO, since SiN can have higher etch selectivity than LTO. Due to its higher etch selectivity, using the SiN spacer can keep the spacer layer thick enough during the hard mask etching to maintain a good metal hard mask profile. However, the SiN spacer layer requires the use of high deposition temperatures, over 400 degrees, which can cause degradation of the mandrel layer formed of an OPL existing directly under the SiN spacer layer.
Another attempt to solve the problem includes using a thicker mandrel layer so that the spacer profile remains high enough even after the SiARC etch back step so the profile of the metal hard mask is not degraded during that etch back step. However, making the mandrel layer thicker results in the profile having a high aspect ratio due to tall narrow spacers. This type of profile makes it difficult to effectively remove the OPL during the OPL removal step. As a result it is necessary to aggressively over etch during the OPL removal step causing the OPL mask to shrink in the block area generating pattern defect issues. If over etching is not preformed some of the OPL remains between the spacers which can lead to faulty patterning in the hard mask layer which can prevent some trenches from being properly formed.
Accordingly, there is a need to improve the metal hard mask etching profile produced during SIT patterning processes to increase the yield and reliability of semiconductor devices.